TSMC: AI Chip Fabrication and Advanced Packaging

Manufacturing the design

Morris Chang established TSMC in 1987 around the pure-play foundry model: manufacture customers’ chips instead of selling a competing line of chip designs. That separation is central to its AI role. A model lab or accelerator company can specify a processor while relying on TSMC’s manufacturing processes and factories to turn the design into silicon. [1]

NVIDIA’s October 17, 2025 announcement provides a concrete example. It described Blackwell wafer production at TSMC’s Phoenix facility and a ceremony marking the first Blackwell wafer produced in the United States. TSMC manufactured the wafer for NVIDIA’s architecture; the announcement did not establish that every step from wafer to finished AI system had moved to the United States. [3]

Connecting the pieces

TSMC also supplies advanced packaging. Its 3DFabric portfolio includes chip-stacking and packaging technologies such as CoWoS, with services that coordinate chips, substrates and memory. This extends its role beyond making an individual logic die: the package must connect components into the system the customer designed. A processor design therefore depends on the foundry’s integration services as well as its wafer process. [2]

A reported OpenAI program

The Atlas also records Reuters’ October 2024 report about an OpenAI chip program. Reuters said OpenAI was developing the design with Broadcom and had secured manufacturing capacity at TSMC through Broadcom for a tentative 2026 target. OpenAI and TSMC declined comment. This was reporting about a planned program, not a chip release, and it does not establish that TSMC was designing OpenAI’s processor. [4]